(1) Field of the Invention
The present invention relates to the fabrication of a novel MOSFET for integrated circuit devices on semiconductor substrates, and more particularly relates to a MOSFET structure having reduced channel lengths without reducing the gate suicide areas, and having improved short-channel effects including reduced gate-to-drain capacitance and improved source-to-drain punchthrough.
(2) Description of the Prior Art
Advances in the semiconductor process technologies in the past few years have dramatically decreased the device feature sizes and increased circuit density on integrated circuit chips. The device most used for Ultra Large Scale Integration (ULSI) is the Field Effect Transistor (FET), having a silicon or silicon and metal-silicide (polycide) gate electrode with self-aligned source/drain contact areas. Commonly referred to as MOSFETs (Metal-Oxide-Silicon FETs) because of the early use of a metal as the gate electrode, these three terminal devices are now made using polycide for the gate electrodes, and more recently use shallow silicide contacts for the source/drain areas. The popular choice of FETs is because of their low cost, very small size, high packing density, low power consumption, and high yields.
The conventional FETs are typically fabricated by patterning polysilicon gate electrodes over a thin gate oxide on a single-crystal semiconductor substrate. The gate electrode structure is used as a diffusion or implant barrier mask to form self-aligned source/drain areas in the substrate adjacent to the sides of the gate electrodes. The distance from the source junction to drain junction under the gate electrodes is defined as the channel length of the FET.
Advances in semiconductor technologies, such as high-resolution photolithographic techniques and anisotropic plasma etching, to name a few, have reduced the minimum feature sizes of devices to much less than a micrometer. Currently in the industry, FETs are made having channel lengths that are less than a quarter-micrometer (about 0.25 um) in length, and in future product the channel length is expected to decrease further to 0.18 um and less.
However, as this downscaling continues and the channel length is further reduced, the FET device experiences a number of undesirable electrical characteristics known as short channel effects (SCE). These short channel effects become more severe as the device physical dimensions and, more specifically, as the FET channel length is scaled down. This result is due to the fact that the band gap and built-in potential at junctions are an intrinsic property (constant) of the crystalline materials (such as silicon), and are non-scalable with the further reduction in device dimensions.
These adverse short channel effects result from the electric field distribution in the channel area when the integrated circuit is powered up, which lead to a number of problems. For example, electrons ejected from the drain can acquire sufficient energy to be injected into the gate oxide resulting in charge buildup in the oxide that causes threshold voltage shifts. Unfortunately, this hot carrier effect (HCE) can degrade device performance after the product is in use (at the customer). Other effects that can limit device performance are the parasitic capacitance, such as gate-to-drain capacitance, fringing capacitance at the edge of the gate electrode, and the junction capacitance at the source/drain diffused junctions.
One method of minimizing these short channel effects, common practice in the semiconductor industry, is to fabricate FET structures with Lightly Doped Drains (LDDs). These LDD FET structures have low dopant concentrations in the drain regions adjacent to the gate electrodes, and modify the electric fields in the drains so as to minimize or eliminate short channel effects, such as hot carrier effects. Another problem is punchthrough between the source and drain as the channel length is scaled down. Typically an anti-punchthrough implant is introduced in the substrate under the gate oxide to minimize this effect.
The LDD FETs are typically formed by using two ion implantations. After forming the polysilicon gate electrodes, a first implant, using the gate electrodes as an implant mask, is carried out to form lightly doped source/drain regions adjacent to the gate electrodes. Sidewall spacers are then formed on the gate electrodes and a second implant is used to form the heavily doped source/drain regions.
Several methods of improving the FET electrical characteristics have been reported in the literature. One method is reported in a paper titled "A Gate-Side Air-Gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETS" in VLSI Technical Proceedings, 1996, on page 38. In this paper, the advantage of using an air gap between the side of the gate electrode and the sidewall spacer to reduce capacitance between the gate and drain (C.sub.gd), commonly referred to as Miller capacitance, to improve the gate delay time was reported.
Several methods for making FETs with air gaps include U.S. Pat. No. 5,869,374 to Wu, U.S. Pat. No. 5,869,479 to Gardner et al., and U.S. Pat. No. 5,736,446 to Wu.
However, there is still a strong need in the semiconductor industry to further improve the electrical characteristics as the FET channel length continues to decrease below 0.25 um, and still maintaining a cost-effective manufacturing process.